Microprocessors, and other clocked logic circuits, commonly use an internal clock derived from an external input clock--such as a computer system clock--to permit synchronous operations. Clock multiplication is used in current microprocessor designs to achieve performance increases by increasing the internal CPU clock relative to the external system clock.
Without limiting the scope of the invention, this background information is provided in the context of a specific problem to which the invention has application: in a microprocessor, an improved technique for generating an internal clock that is higher in frequency than the input system clock, and that has a duty cycle that does not depend on the duty cycle of the system clock.
In computer systems using the 386 bus architecture, the microprocessor receives an external system clock that is twice the internal CPU clock (CLK2)--the microprocessor divides CLK2 to obtain a clean internal CPU clock (CLK) with well-defined transitions and duty cycle. In later generation computer systems using the 486 bus architecture, the microprocessor conventionally operates in what is called a 1X clock mode, with the internal CPU clock being at the same frequency as the external computer system clock. Phase lock loop (PLL) circuitry in combination with divide-by-two logic is used to obtain a CPU clock that is stable relative to the input clock frequency and has a 50--50 duty cycle. To enhance performance of these 486-bus computer systems without requiring an increase in the computer system clock, some 486-type microprocessors employ a technique called "clock doubling" in which the microprocessor includes clock multiplication circuitry to generate an internal CPU clock that is twice the frequency of the input clock from the computer system. In these microprocessors, the CPU core runs at the 2X clock rate while the bus interface logic operates at the 1X clock rate used by the computer system.
Current clock multiplication techniques typically employ phase locked loop (PLL) circuits in combination with frequency divider logic--the ratio of the frequency dividers in the output and feedback loops determines the relative frequency between the generated clock signals and the input clock frequency.
This clock multiplication approach is disadvantageous in several respects. PLL circuits are generally limited in operating power supply voltage range, and therefore are not well suited for microprocessors designed to operate with both 5 volt and 3.3 volt power supplies. Moreover, PLL circuits do not support switching between different clock rates (including clock stopping to preserve power) because exceeding a specified slew rate will cause a PLL to drop frequency lock. In addition, the use of frequency division to control duty cycle does not provide much flexibility in controlling the duration of both phases of the clock signal. Accordingly, a specific object of the invention is to provide an improved clock multiplier circuit for a microprocessor capable of generating a higher frequency CPU clock with a duty cycle that does not depend on the input clock duty cycle. A more general object is to implement clock multiplication using one or more delay lines to generate a selected number of transitions between the active edges of an input clock, each defining a clock phase of a selected duration.